1. Technical Field of the Invention
The present invention relates generally to application specific integrated circuit (ASIC) memories and more specifically to a method and an apparatus for repairing memory faults within an ASIC chip.
2. Description of the Background Art
It is common practice for the manufacturers of ASIC chips to test the functionality of the ASIC memories at the manufacturing site. After the chips have been tested and certified for shipment upon sale to the users, the users generally depend upon the reliability of the chips for their own system design to function properly. As the density and line width of memory cells within a memory array circuit chip continue to shrink (now at less than one-half micron), this reliability becomes more difficult to attain. The challenges for manufacturers of ASIC chips is to increase memory capacity without decreasing the chip yields.
Before the ASIC chips are released for shipment, they typically undergo testing to verify that each of the memory cells within the memory array is functioning properly. This testing method is routinely done because it is not uncommon for a large percentage of the memory cells within the ASIC chips to fail, including manufacturing defects and degradation faults.
In the past, ASIC memories have been tested using an external memory tester or Automatic Test Equipment (ATE)) at the manufacturing site. This testing technique is not available to users once the chips have been shipped, making it difficult to detect faulty memory cells at the user site. Even if test equipment is available to users, field repairs are expensive, time consuming, and impractical.
In addition, some repairs of ASIC memories have also been performed at the manufacturing site. Conventional repairing techniques bypass the defective cells by hardwiring through fuzable links using laser techniques that cause address redirection. However, these techniques are limited to one-time repair and require significant capital investment for implementing the technical complexity of the repairing process because the test patterns must pass through several layers of mask logic.
In sum, ASIC memories have been tested and repaired at the manufacturer site using fuse/antifuse techniques to detect the location of defects and to perform repairs as part of the manufacturing process. These techniques are costly and leave the semiconductor chips useless if the memories become defective after shipment from the manufacturing site.
Hence, there is a need to provide on-chip test and repair techniques to fix faulty ASIC memories.